![]() ![]() 't imescale 100ms / 1ms module enable_flash( input clk, input switch, output led ) Īm I wrong that the clock signal will always be 100MHz and then I need to manipulate it in my sources (.v) file? v file, but then going into the constraints file, I think that Artix-7 is going to feed a 100MHz clock in no matter what timescale i choose. Initially, I thought I could create the clock signal just by editing the 'timescale line at the top of my. Essentially, I want to generate a simple blinking LED at a perceptible freq (say, 10Hz / 100ms). I realize I have a gap in knowledge with what im trying to do. If it isn't obvious already, I'm new to FPGA.moving on.
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